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System Architecture
Table 2-1. Signals of Expansion Interface Connectors (Cont’d)
Net/Bus Name
(Direction)
MISO
(Output)
RSCLK0
(Bi)
RFS0
(Bi)
DR0PRI
(Output)
DR0SEC
(Output)
TSCLK0
(Bi)
TFS0
(Bi)
DT0PRI
(Input)
DT0SEC
(Input)
A-V EZ-Extender Function
The SPI serial input data signal used to read the control
register of the AD1836A audio codec.
Processor’s SPORT0 receive clock signal connected to the
serial clock on the digital side of the audio codec analog
input. In I 2 S mode, the signal can connect to the TSCLK0
net.
Processor’s SPORT0 receive frame sync signal connected
to the frame sync on the digital side of the audio codec
analog input. In I 2 S mode, the signal can connect to the
TFS0 net.
Connection to the data output of the audio codec; can be
disconnected with a jumper if the signal is needed for
another purpose.
Secondary connection to the data output of the audio
codec. Can be disconnected with a jumper if the signal is
needed to be used for another purpose.
Processor’s SPORT0 transmit clock signal; connects to the
serial clock on the digital side of the audio codec’s analog
output. In I 2 S mode, the signal can connect to the
RSCLK0 net.
Processor’s SPORT0 transmit frame sync signal. Connects
to the frame sync on the digital side of the audio codec
analog output. In I 2 S mode, the signal can connect to the
RFS0 net.
Connection to the data input of the audio codec.
Secondary connection to the data input of the audio
codec.
Relevant
Configuration
Jumpers
JP7.1/2
JP7.1/2
JP7.3/4
JP7.5/6
JP7.1/2
JP7.1/2
2-6
Blackfin A-V EZ-Extender Manual
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